1. Field
The disclosed embodiments relate to networks of components in computer systems. More specifically, the disclosed embodiments relate to techniques for limiting bandwidth for write transactions transmitted by the components across the networks.
2. Related Art
A modern computer system typically includes a motherboard containing a processor and memory, along with a set of peripheral components connected to the motherboard via a variety of interfaces. For example, a Serial Advanced Technology Attachment (SATA) interface may facilitate data transfer between a storage device (e.g., hard disk drive, optical drive, solid-state drive, hybrid hard drive, etc.) and the motherboard, while a Peripheral Component Interconnect Express (PCIe) bus may enable communication between the motherboard and a number of integrated and/or add-on peripheral components.
In addition, the throughputs and/or latencies of the interfaces may affect the rates at which data is transferred between components in computer systems. For example, a PCIe interface may correspond to a network that connects a set of components in the computer system using a set of switches. The switches may merge transactions from peripheral components to the root complex, or chipset, of the computer system. As a result, transactions from an aggressive peripheral component to the root complex may consume available bandwidth on switches between the peripheral component and the root complex, causing other peripheral components connected to the same switches to experience increased latency on the network and, in turn, reduced performance.
Hence, what is needed is a mechanism for limiting bandwidth and/or performing load balancing for transactions transmitted across networks of components in computer systems.